View Z16C32SL1660_8144966.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cp97hhs0100 p r e l i m i n a r y 1-1 1 p reliminary c ustomer p rocurement s pecification z16c32 sl1660 o nly 1 iusc i ntegrated u niversal s erial c ontroller general description the iusc (integrated universal serial controller) is a sin- gle-channel multple protocol data communications device with on-chip dual-channel dma. the integration of a high- speed serial communications channel with a high perfor- mance dma facilitates higher data throughput than is pos- sible with discrete serial/dma chip combinations. the buff- er chaining capabilities combined with features like character counters, frame status block and buffer termina- tion at the end of the frame facilitate sophisticated buffer management that can significantly reduce cpu overhead. the iusc is software configurable to satisfy a wide variety of serial communications applications. offered at 20 mbit/sec, its fast data transfer rate and multiple protocol support make it ideal for applications in todays dynamic environment of changing specifications and ever increas- ing speed. the many programmable features allow the user to tune the device response to meet system require- ments and adapt to future changes with software instead of redesigning hardware. the on-chip dma channels allow high-speed data trans- fers for both the receiver and the transmitter. the device supports automatic status transfer through dma and al- lows device initialization under dma control. each dma channel can transfer data words in as little as three 50 ns clock cycles and can generate addresses compatible with 32-, 24- or 16-bit memory ranges. the dma channels may operate in any of four modes: single buffer, pipelined, ar- ray-chained, or linked-list. the array-chained and linked- list modes reduce the problems with segmentation and re- assembly of messages in systems. to prevent the dma from holding bus mastership too long, mastership time may be limited by counting the absolute number of clock cycles, the number of bus transactions, or both. the cpu bus interface is designed for use with any con- ventional multiplexed or non-multiplexed bus. the device contains a variety of sophisticated internal functions includ- ing two baud rate generators, a digital phase-locked loop, character counters, and 32-byte fifos for both the receiv- er and transmitter. the iusc handles asynchronous formats, synchronous byte-oriented formats (e.g., bisync), and synchronous bit-oriented formats such as hdlc. this device supports virtually any serial data transfer application. the iusc can generate, and check crc in any synchro- nous mode and is programmed to check data integrity in various modes. access to the crc value allows system software to resend or manipulate it as needed in various applications. the iusc also has facilities for modem con- trols. in applications where these controls are not needed, the modem controls can be used for general-purpose i/o. interrupts are supported by a daisy-chain hierarchy within the serial channel and between the serial channel and the dma. support tools are available to aid the designer in efficiently programming the iusc. the technical manual describes in detail all features presented in this product specification and gives programming sequence hints. the epm man- ual (electronic programmers manual) is an ms-dos, disk- based programming initialization tool, used in conjunction with the technical manual. also, there are assorted appli- cation notes and development boards to assist the design- er in hardware/software development. notes: all signals with a preceding front slash, "/", are active low. for example, b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions below: connection circuit device power v cc v dd ground gnd v ss
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-2 p r e l i m i n a r y cp97hhs0100 . figure 1. iusc block diagram bus interface transmit dma transmit fifo host processor interrupt control transmitter time slot assigner receive dma serial clock logic dpll counters brg0, brg1 receiver time slot assigner receive fifo i/o port 16-bit internal data bus
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-3 1 figure 2. plcc 68-pin assignments 60 44 10 26 /abort /int iei ieo gnd vcc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd vcc /rxreq b//w /wait//rdy reserved s//d d//c /cs /reset vcc vcc vcc /as /ds /rd /wr r//w /intack /uas 43 27 61 9 plcc 68 - pin 1 /bin /busreq clk /bout gnd vcc ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 gnd vcc port 7 /txreq /rxc /rxd /dcd /txc /txd /cts gnd gnd gnd port 0 port 1 port 2 port 3 port 4 port 5 port 6
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-4 p r e l i m i n a r y cp97hhs0100 figure 3. qfp 80-pin assignments 40 25 65 80 /uas /intack r/w /wr /rd /ds /as vcc vcc nc /reset /cs d//c s//d /wait//rdy b//w port 6 port 5 port 4 port 3 port 2 port 1 port 0 gnd gnd /cts txd /txc /dcd rxd /rxc /txreq nc nc nc /abort nc /int iei ieo gnd vcc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd vcc /rxreq nc nc nc nc nc nc /bin nc /bus req clk /bout gnd vcc ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 gnd vcc nc nc nc port 7 5101520 24 60 55 50 45 41 64 qfp 80 - pin 1
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-5 1 figure 4. functional diagram ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 /as /ds /rd /wr /cs s//d d//c r//w /intack /wait//rdy gnd gnd gnd gnd gnd gnd gnd txd rxd /txc /rxc /cts /dcd /rxreq /abort /txreq b//w /int iei ieo port 0 port 1 serial data channel clocks channel i/o channel dma interface device reset port 2 port 3 port 4 port 5 port 6 port 7 /reset vcc vcc vcc vcc vcc vcc vcc channel interrupt ground interrupt control bus timing address/ data bus i/o port power clk system clock /busreq /bin /bout /uas z16c32
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-6 p r e l i m i n a r y cp97hhs0100 absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. standard test conditions the dc characteristics and capacitance section below apply for the following standard test conditions, unless otherwise noted. all voltages are referenced to gnd. positive current flows into the referenced pin (standard test load). standard conditions are as follows: n +4.5 v < v cc < +5.5 v n gnd = 0 v n t a as specified in ordering information capacitance miscellaneous transistor count - 100,000 temperature range standard: 0 c to +70 c sym description min max unit v cc supply voltage -0.3 +70 v t stg storage temp 65 +150 c t a operating ambient temp 0 +70 c figure 5. standard test load +5v from output under test 50 pf 250 m a 1.73 k w symbol parameter min max unit condition c in input capacitance 10 pf unmeasured pins returned to ground. c out output capacitance 15 pf c i/o bidirectional capacitance 20 pf note: f = 1 mhz, over specified temperature range.
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-7 1 dc characteristics ac characteristics timing diagrams v cc t a = 0 c to +70 c symbol parameter min typ max unit condition v ih input high voltage 2.2 v cc +0.3 v v il input low voltage ?.3 0.8 v v oh1 output high voltage 2.4 v i oh = ?.6ma v oh2 output high voltage v cc ?.8 v i oh = ?50 m a v ol output low voltage 0.4 v i ol = +2.0 ma i il input leakage +10.00 m a 0.4 < v in < +2.4v i ol output leakage +10.00 m a 0.4 < v out < +2.4v i cc1 v cc supply current 7 50 ma v cc =5v v ih =4.8v v il = 0.2v note: v cc = 5v 10% unless otherwise specified, over specified temperature range. figure 6. reset timing /reset /stb 113 114 115 figure 7. bus cycle timing 112 1 1 /stb note : /stb is any of the following: /ds, /rd, /wd or pulsed /intack.
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-8 p r e l i m i n a r y cp97hhs0100 ac characteristics (continued) figure 8. multiplexed /ds read cycle /cs 12 13 14 15 17 16 2 6 3 1 20 21 4 5 18 19 8 9 10 11 23 22 116 79 80 7 s//d, d//c /intack (status) /as r//w /ds ad15-ad0 /rxreq /wait//rdy (wait) /wait//rdy (ready)
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-9 1 figure 9. multiplexed /ds write cycle /cs 12 13 14 15 17 16 2 6 1 20 21 4 5 18 19 27 26 116 80 7 s//d, d//c /intack (status) /as r//w /ds ad15-ad0 /txreq /wait//rdy (wait) /wait//rdy (ready) 25 24
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-10 p r e l i m i n a r y cp97hhs0100 ac characteristics (continued) figure 10. multiplexed double-pulse intack cycle /wait//rdy (ready) /wait//rdy (wait) /intack (2-pulse) ad15-ad0 iei ieo /int 83 105 109 103 108 102 101 104 88 106 110 79 107 100 97 96 97 96 18 19 2 99 2 1 1 98 18 19 99 98 /as
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-11 1 figure 11. memory read clk /uas /as /ds r//w /rd s//d, d//c ad15-ad0 /wait//rdy (wait) /wait//rdy (ready) /bin 120 125 127 126 128 129 130 131 132 137 138 144 149 150 151 152 148 145 146 147 153 155 172 173 156 154 139 141 140 143 142 134 133 135 136 121 122 /abort 168 169 123 124
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-12 p r e l i m i n a r y cp97hhs0100 ac characteristics (continued) figure 12. memory write clk /uas /as /ds r//w /wr s//d, d//c ad15-ad0 /wait//rdy (ready) /wait//rdy (wait) /bin 120 125 127 126 128 129 130 137 144 149 150 151 145 145 153 155 172 173 156 154 121 122 159 161 134 160 134 158 163 166 166 164 165 162 152 145 157 123 124 /abort 168 169
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-13 1 ac characteristics timing table v cc t a = 0 c to +70 c no symbol parameter min max units note(s) 1 tcyc bus cycle time 110 ns 2 twasl /as low width 30 ns 3 twash /as high width 60 ns 4 twdsl /ds low width 60 ns 5 twdsh /ds high width 50 ns 6 tdas(ds) /as rise to /ds fall delay time 5 ns 7 tdds(as) /ds rise to /as fall delay time 5 ns 8 tdds(dra) /ds fall to data active delay 0 ns 9 tdds(drv) /ds fall to data valid delay 60 ns 10 tdds(drn) /ds rise to data not valid delay 0 ns 11 tdds(drz) /ds rise to data float delay 20 ns 12 tscs(as) /cs to /as rise setup time 15 ns 13 thcs(as) /cs to /as rise hold time 5 ns 14 tsadd(as) direct address to /as rise setup time 15 ns 1 15 thadd(as) direct address to /as rise hold time 5 ns 1 16 tssia(as) status /intack to /as rise setup time 15 ns 17 thsia(as) status /intack to /as rise hold time 5 ns 18 tsad(as) address to /as rise setup time 15 ns 19 thad(as) address to /as rise hold time 5 ns 20 tsrw(ds) r//w to /ds fall setup time 0 ns 21 thrw(ds) r//w to /ds fall hold time 25 ns 22 tsdsf(rrq) /ds fall to /rxreq inactive delay 60 ns 4 23 tddsr(rrq) /ds rise to /rxreq active delay 0 ns 24 tsdw(ds) write data to /ds rise setup time 30 ns 25 thdw(ds) write data to ds rise hold time 0 ns 26 tddsf(trq) /ds fall to /txreq inactive delay 65 ns 5 27 tddsr(trq) /ds rise to /txreq active delay 0 ns 28 twrdl /rd low width 60 ns 29 twrdh /rd high width 50 ns 30 tdas(rd) /as rise to /rd fall delay time 5 ns 31 tdrd(as) /rd rise to /as fall delay time 5 ns 32 tdrd(dra) /rd fall to data active delay 0 ns 33 tdrd(drv) /rd fall to data valid delay 60 ns 34 tdrd(drn) /rd rise to data not valid delay 0 ns 35 tdrd(drz) /rd rise to data float delay 20 ns 36 tdrdf(rrq) /rd fall to /rxreq inactive delay 60 ns 4 37 tdrdr(rrq) /rd rise to /rxreq active delay 0 ns 38 twwrl /wr low width 60 ns 39 twwrh /wr high width 50 ns 40 tdas(wr) /as rise to /wr fall delay time 5 ns 41 tdwr(as) /wr rise to /as fall delay time 5 ns 42 tsdw(wr) write data to /wr rise setup time 30 ns 43 thdw(wr) write data to /wr rise hold time 0 ns 44 tdwrf(trq) /wr fall to /txreq inactive delay 65 ns 5
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-14 p r e l i m i n a r y cp97hhs0100 45 tdwrr(trq) /wr rise to /txreq active delay 0 ns 46 tscs(ds) /cs to /ds fall setup time 0 ns 2 47 thcs(ds) /cs to /ds fall hold time 25 ns 2 48 tsadd(ds) direct address to /ds fall setup time 5 ns 1,2 49 thadd(ds) direct address to /ds fall hold time 25 ns 1,2 50 tssia(ds) status /intack to /ds fall setup time 5 ns 2 51 thsia(ds) status /intack to /ds fall hold time 25 ns 2 52 tscs(rd) /cs to /rd fall setup time 0 ns 2 53 thcs(rd) /cs to /rd fall hold time 25 ns 2 54 tsadd(rd) direct address to /rd fall setup time 5 ns 1,2 55 thadd(rd) direct address to /rd fall hold time 25 ns 1,2 56 tssia(rd) status /intack to /rd fall setup time 5 ns 2 57 thsia(rd) status /intack to /rd fall hold time 25 ns 2 58 tscs(wr) /cs to /wr fall setup time 0 ns 2 59 thcs(wr) /cs to /wr fall hold time 25 ns 2 60 tsadd(wr) direct address to /wr fall setup time 5 ns 1,2 61 thadd(wr) direct address to /wr fall hold time 25 ns 1,2 62 tssia(wr) status /intack to /wr fall setup time 5 ns 2 63 thsia(wr) status /intack to /wr fall hold time 25 ns 2 78 tddsf(rdy) /ds fall (intack) to /rdy fall delay 200 ns 79 tdrdy(drv) /rdy fall to data valid delay 40 ns 80 tddsr(rdy) /ds rise to /rdy rise delay 40 ns 81 tsiei(dsi) iei to /ds fall (intack) setup time 10 ns 82 thiei(dsi) iei to /ds rise (intack) hold time 0 ns 83 tdiei(ieo) iei to ieo delay 30 ns 84 tdas(ieo) /as rise (intack) to ieo delay 60 ns 85 tddsi(int) /ds fall to /int inactive delay 200 ns 86 tddsi(wf) /ds fall (intack) to /wait fall delay 40 ns 87 tddsi(wr) /ds fall (intack) to /wait rise delay 200 ns 88 tdw(drv) /wait rise to data valid delay 40 ns 89 tdrdf(rdy) /rd fall (intack) to /rdy fall delay 200 ns 90 tdrdr(rdy) /rd rise to /rdy rise delay 40 ns 91 tsiei(rdi) iei to /rd fall (intack) setup time 10 ns 92 thiei(rdi) iei to /rd rise (intack) hold time 0 ns 93 tdrdi(int) /rd fall (intack) to /int inactive delay 200 ns 94 tdrdi(wf) /rd fall (intack) to /wait fall delay 40 ns 95 tdrdi(wr) /rd fall (intack) to /wait rise delay 200 ns 96 twpial pulsed /intack low width 60 ns 97 twpiah pulsed /intack high width 50 ns 98 tdas(pia) /as rise to pulsed /intack fall delay time 5 ns 99 tdpia(as) pulsed /intack rise to /as fall delay time 5 ns 100 tdpia(dra) pulsed /intack fall to data active delay 0 ns 101 tdpia(drn) pulsed /intack rise to data not valid delay 0 ns 102 tdpia(drz) pulsed /intack rise to data float delay 20 ns 103 tsiei(pia) iei to pulsed /intack fall setup time 10 ns 104 thiei(pia) iei to pulsed /intack rise hold time 0 ns v cc t a = 0 c to +70 c no symbol parameter min max units note(s)
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-15 1 105 tdpia(ieo) pulsed /intack fall to ieo delay 60 ns 106 tdpia(int) pulsed /intack fall to /int inactive delay 200 ns 107 tdpiaf(rdy) pulsed /intack fall to /rdy fall delay 200 ns 108 tdpiar(rdy) pulsed /intack rise to /rdy rise delay 40 ns 109 tdpia(wf) pulsed /intack fall to /wait fall delay 40 ns 110 tdpia(wr) pulsed /intack fall to /wait rise delay 200 ns 111 tdsia(int) status /intack fall to ieo inactive delay 200 ns 2 112 twstbh /strobe high width 50 ns 3 113 twresl /reset low width 170 ns 114 twresh /reset high width 60 ns 115 tdres(stb) /reset rise to /stb fall 60 ns 3 116 tddsf(rdy) /ds fall to /rdy fall delay 50 ns 117 tdwrf(rdy) /wr fall to /rdy fall delay 50 ns 118 tdwrr(rdy) /wr rise to /rdy rise delay 40 ns 119 tdrdf(rdy) /rd fall to /rdy fall delay 50 ns 120 twclkl clk low width 25 ns 121 twclkh clk high width 25 ns 122 tcclk clk cycle time 50 ns 123 tfclk clk fall time 5 ns 124 trclk clk rise time 5 ns 125 tdclkr (uas) clk rise to /uas fall delay 25 ns 6 126 twuasl /uas low width 20 ns 6,7 127 tdclkf(uas) clk fall to /uas rise delay 25 ns 6 128 tdclkr(as) clk rise to /as fall delay 25 ns 6 129 twasl /as low width 20 ns 6,7 130 tdclkf(as) clk fall to /as rise delay 25 ns 6 131 tdas(dsr) /as rise to /ds fall (read) delay 20 ns 6,8 132 tdclkr(ds) clk rise to /ds delay 25 ns 6 133 twdslr /ds (read) low width 70 ns 6,9 134 tdclkf(ds) clk fall to /ds delay 25 ns 6 135 tsdr(ds) read data to /ds rise setup time 30 ns 6 136 thdr(ds) read data to /ds rise hold time 0 ns 6 137 tdclk(rw) clk rise to r//w delay 25 ns 6 138 tdas(rd) /as rise to /rd fall delay 20 ns 6,8 139 tdclkr(rd) clk rise to /rd delay 25 ns 6 140 twrdl /rd low width 70 ns 6,9 141 tdclkf(rd) clk fall to /rd delay 25 ns 6 142 tsdr(rd) read data to /rd rise setup time 30 ns 6 143 thdr(rd) read data to /rd rise hold time 0 ns 6 144 tdclk(add) clk rise to direct address delay 25 ns 1,6 145 tdclk(ad) clk rise to address delay tdclkf(ds) 25 ns 6 146 thad(pc) address to clk rise hold time 0 ns 6 147 tdclk(adz) clk rise to address float delay 25 ns 6 148 tdclk(ada) clk rise to address active delay 25 ns 6 149 tsad(uas) address to /uas rise setup time 10 ns 6 150 thad(uas) address to /uas rise hold time 10 ns 6 v cc t a = 0 c to +70 c no symbol parameter min max units note(s)
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-16 p r e l i m i n a r y cp97hhs0100 151 tsad(as) address to /as rise setup time 10 ns 6 152 thad(as) address to /as rise hold time 10 ns 6 153 tsw(clk) /wait to clk fall setup time 10 ns 6 154 thw(clk) /wait to clk fall hold time 15 ns 6 155 tsrdy(clk) /ready to clk fall setup time 10 ns 6 156 thrdy(clk) /ready to clk fall hold time 15 ns 6 157 thdw(clk) write data to clk rise hold time 0 ns 6 158 tdas(dsw) /as rise to /ds fall (write) delay 40 ns 6,10 159 tsdw(ds) write data to /ds fall setup time 20 ns 6, 7 160 twdslw /ds (write) low width 45 ns 6, 11 161 thdw(ds) write data to /ds rise hold time 20 ns 6, 8 162 tdas(wr) /as rise to /wr fall delay 40 ns 6, 10 163 tsdw(wr) write data to /wr fall setup time 20 ns 6, 7 164 twwrl /wr low width 45 ns 6, 11 165 thdw(wr) write data to /wr rise hold time 20 ns 6, 8 166 tdclk(wr) clk fall to /wr delay 25 ns 6 167 tdclk(busz) clk rise to bus float delay 25 ns 6 168 tsabt(clk) /abort to clk rise setup time 20 ns 6 169 thabt(clk) /abort to clk rise hold time 15 ns 6 170 tdclk(brq) clk rise to /busreq delay 25 ns 6 171 tdclk(busa) clk rise to bus active delay 25 ns 6 172 tsbin(clk) /bin to clk rise setup time 20 ns 6 173 thbin(clk) /bin to clk rise hold time 15 ns 6 174 tsbrq(clk) /busreq to clk rise setup time 25 ns 6 175 thbrq(clk) /busreq to clk rise hold time 0 ns 6 176 tdbin(bot) /bin to /bout delay 60 ns notes: ac test conditions: v cc = 5v 10% unless otherwise specified, over specified temperature range. v ih = 2.0v voh = 2.0v v il = 0.8v vol = 0.8v float = +0.5v 1. direct address is any of s//d, d//c or ad15-ad8 used as an address bus. 2. the parameter applies only when /as is not present. 3. strobe is any of /ds, /rd, /wr or pulsed /intack. 4. parameter applies only if read empties the receive fifo. 5. parameter applies only if write fills the transmit fifo. 6. parameter applies only while the iusc is bus master. 7. parameter is clock-cycle dependent, twclkh + tfclk - 5. 8. parameter is clock-cycle dependent, twclkl + trclk - 5. 9. parameter is clock-cycle dependent, tcclk + twclkh + tfclk - 5. 10. parameter is clock-cycle dependent, tcclk - 10. 11. parameter is clock-cycle dependent, tcclk -5. values shown for parameters with notes 7, 8, 9, 10, or 11 are calculated using corresponding equations with minimum values. v cc t a = 0 c to +70 c no symbol parameter min max units note(s)
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-17 1 ac characteristics general timing diagram figure 13. general timing /dcd as /sync external /txc /rxc, /txc receive rxd /txc, /rxc transmit txd /rxc 1 3 5 6 8 7 11 9 10 12 14 13 15 15 16 16 /cts, /dcd /dcd as /sync input 4 2
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-18 p r e l i m i n a r y cp97hhs0100 ac characteristics general timing table ac characteristics system timing table t a = 0 c to +70 c no symbol parameter min max units note(s) 1 tsrxd(rxcr) rxd to /rxc rise setup time (x1 mode) 0 ns 1 2 thrxd(rxcr) rxd to /rxc rise hold time (x1 mode) 20 ns 1 3 tsrxd(rxcf) rxd to /rxc fall setup time (x1 mode) 0 ns 1,3 4 thrxd(rxcf) rxd to /rxc fall hold time (x1 mode) 20 ns 1,3 5 tssy(rxc) /dcd as /sync to /rxc rise setup time 0 ns 1 6 thsy(rxc) /dcd as /sync to /rxc rise hold time (x1 mode) 20 ns 1 7 tdtxcf(txd) /txc fall to txd delay 35 ns 2 8 tdtxcr(txd) /txc rise to txd delay 35 ns 2,3 9 twrxch /rxc high width 20 ns 10 twrxcl /rxc low width 20 ns 11 tcrxc /rxc cycle time 50 ns 12 twtxch /txc high width 20 ns 13 twtxcl /txc low width 20 ns 14 tctxc /txc cycle time 50 ns 15 twext /dcd or /cts pulse width 35 ns 16 twsy /dcd as /sync input pulse width 35 ns t a = 0 c to +70 c no symbol parameter min max units note 1 tdrxc(req) /rxc rise to /rxreq valid delay 50 ns 2 2 tdrxc(rxc) /txc rise to /rxc as receiver output valid delay 50 ns 2 3 tdrxc(int) /rxc rise to /int valid delay 50 ns 2 4 tdtxc(req) /txc fall to /txreq valid delay 50 ns 2 5 tdtxc(txc) /rxc fall to /txc as transmitter output valid delay 50 ns 6 tdtxc(int) /txc fall to /int valid delay 50 ns 2 7 tdext(int) /cts, /dcd, /txreq, /rxreq transition to /int valid delay 50 ns notes: 1. /rxc is /rxc or /txc, whichever is supplying the receive clock. 2. /txc is /txc or /rxc, whichever is supplying the transmit clock. 3. parameter applies only to fm encoding/decoding
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-19 1 iusc technical manual correction there is a typographical error in the q2/91 printing of the iusc technical manual. the transmit and receive inter- rupt pending (ip) and interrupt under service (ius) bits are shown in reverse order. the correct register bit locations are shown below. the correct bit functions are also shown in the iusc product specification. register corrected register bits cdir rxius=d9 txius-d8 rxip=d1 txip=d0 dicr rxie=d1 txie=d0 sdir rxius=d9 txius=d8 rxip=d1 txie=d0
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-20 p r e l i m i n a r y cp97hhs0100 ac characteristics system timing diagram figure 14. z16c32 system timing /rxc, /txc receive 1 2 3 4 5 6 7 /rxreq request /rxc as receiver output /int /rxc, /txc transmit /txreq /txc as transmitter output /int /cts, /dcd, /txreq, /rxreq /int
z16c32 sl1660 only zilog iusc integrated universal serial controller cp97hhs0100 p r e l i m i n a r y 1-21 1 ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com
z16c32 sl1660 only iusc integrated universal serial controller zilog 1-22 p r e l i m i n a r y cp97hhs0100

▲Up To Search▲

Price & Availability of Z16C32SL1660

	To Download Z16C32SL1660 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .